1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory and a method for fabricating the same, which can increase a device packing density of the memory and reduce a step in a cell region and a peripheral circuit.
2. Background of the Related Art
A related art semiconductor memory will be explained with reference to the attached drawings. FIG. 1 illustrates a plan view of a related art semiconductor memory, and FIG. 2 illustrates a system of a unit cell of the related art semiconductor memory. The related art semiconductor memory is provided with source/drain formed at the same height with a channel region, and a gate line formed at a height different from the source/drain.
Referring to FIG. 1, in the plan view, a semiconductor substrate is defined as active regions 1 and device isolation regions which isolate the active regions 1, and a wordline 3 is provided to cross the active region 1 in a short axis direction. The wordlines 3 are provided at fixed intervals, repeatedly. There are source/drain regions 4a and 4b in the active region 1 on both sides of each of the wordlines 3, a bitline contact layer 5 on the active region 1 between adjacent wordlines 3, and a storage node contact layer 6 on the active region 1 between adjacent wordlines 3 having no bitline contact layer 5 formed thereon. The bitline contact layer 5 is provided, not on a center of the active region 1, but at a position away from the center portion in some extent. This is because of difficulty of storage node contact when the bitline passes through the center portion in a memory of COB(Capacitor On Bitline). And a plurality of bitlines 7 are provided in a direction vertical to the wordlines 3.
A system of a unit cell of the related art semiconductor memory having the foregoing plan view will be explained.
Referring to FIG. 2, the unit cell of the related art semiconductor memory is provided with a device isolation layer 22 formed in a device isolation region of a semiconductor substrate 21 for defining an active region, gate electrodes(wordline) 23 formed on the active region, gate sidewalls 24 formed at sides of the gate electrodes 23, source/drain regions 25a and 25b formed in surfaces of the semiconductor substrate 21 on both sides of each of the gate electrodes 23, an interlayer insulating layer 26 formed on an entire surface inclusive of the cell transistor, a bitline 28 formed on the interlayer insulating layer 26 in contact with the source/drain regions 25b at one side of the cell transistor, a first storage node contact plug layer 27a in contact with the source/drain regions 25a at the other side of the cell transistor not in contact with the bitline 28, and a second storage node contact plug layer 27b connected to the first contact plug layer 27a. The layer with a reference numeral 28 shown in a dotted line represents the bitline. The bitline is shown in the dotted line because the bitline is, not on the sectional plane, but spaced from the sectional plane. The gate electrode 23 has a stack of a gate insulating film, a polysilicon layer and a cap insulating layer in succession. In the related art semiconductor memory, as the gate electrode 23 is formed on the surface of the semiconductor substrate 21, the source/drain 25a and 25b are formed at the same height with a channel region that is formed under the gate electrode 23.
However, the related art semiconductor memory has the following problems.
There has been a limitation in a photo processing because a length of the channel of the wordline becomes the shorter as an extent of the device packing advances. However, the related art semiconductor memory failed to suggest a method for solving this problem because the related art semiconductor memory has wordlines running in parallel to the surface of the substrate, that is not favorable for an easy fabrication and yield.
The repeated increase of a height of a cell capacitor for securing a cell capacitance causes to form a great step between the cell and the peripheral region, which makes conduction of following process difficult, and the two times of photo/etching required for storage node contact causes the fabrication process complicated.